Recently, there have been developed ferroelectric memories, called FeRAM (ferroelectric random access memories), in each of which information is held in a ferroelectric capacitor by use of polarization inversion of a ferroelectric material. The ferroelectric memory is a non-volatile memory in which information is not erased even after the power is turned off, and is particularly drawing attention because of its capabilities to achieve high integration, high-speed operation, high durability, and low power consumption.
As a material for a ferroelectric film constituting a ferroelectric capacitor, mainly used is a ferroelectric oxide having a perovskite crystal structure, such as PZT (lead zirconate titanate: PbZr1-xTixO3) or SBT (SrBi2Ta2O9), the residual polarization charge amount of which is as high as approximately 10 μC/cm2 to 30 μC/cm2. It has been known that the ferroelectric characteristic of such a ferroelectric film is deteriorated due to moisture which enters from the outside through an interlayer insulating film having an affinity for moisture, such as a silicon oxide film. The reason for this is considered as follows. Namely, the moisture entered a device is decomposed into hydrogen and oxygen when a substrate is heated to form an interlayer insulating film or a metal interconnection. Then, the hydrogen enters the ferroelectric film and reduces the ferroelectric film and, this causes oxygen defect in the ferroelectric film and thereby lowers the crystallinity in the ferroelectric film.
Similarly, long term use of a ferroelectric memory also leads to a deterioration of the ferroelectric characteristic of the ferroelectric film, and consequently a deterioration of the performance of the ferroelectric capacitor. Furthermore, in some cases, this also results in a deterioration of the performance of a transistor or the like in addition to the ferroelectric capacitor.
To deal with these problems, in a ferroelectric device such as a FeRAM, a capacitor protection insulating film such as an alumina (Al2O3) film is generally formed in order to prevent moisture or hydrogen from entering a ferroelectric capacitor.
Such a capacitor protection insulating film is disclosed in, for example, Japanese Laid-open Patent Publication No. 2006-49795.
FIG. 1 is an enlarged cross-sectional view of an essential part of a semiconductor device disclosed in the Japanese Laid-open Patent Publication No. 2006-49795.
This semiconductor device includes a ferroelectric capacitor Q formed on a first interlayer insulating film 201 over a semiconductor substrate 200. The ferroelectric capacitor Q includes a lower electrode 202, a capacitor dielectric film 203 made of a ferroelectric material, and an upper electrode 204 stacked in this order.
A capacitor protection insulating film 210 is formed on a second interlayer insulating film 206 made of a silicon oxide covering the ferroelectric capacitor Q. The capacitor protection insulating film 210 serves to prevent hydrogen or moisture from entering the ferroelectric capacitor Q.
Furthermore, holes 206a and 206b for electric connections are formed in each of the insulating films 201, 206, and 210. Conductive plugs 211a and 211b are respectively filled in these holes.
According to the Japanese Laid-open Patent Publication No. 2006-49795, as the capacitor protection insulating film 210, a stacked film of an alumina film 207, a silicon nitride film 208, and an alumina film 209 is formed. The Japanese Laid-open Patent Publication No. 2006-49795 teaches that the silicon nitride film 208 eases stresses in the alumna films 207 and 209.
However, in such capacitor protection insulating film 210, the silicon nitride film 208 functions as a stopper for etching when the holes 206a and 206b are formed by etching. Accordingly, the etching needs a long period of time and also the diameters of the holes 206a and 206b become extremely small below the silicon nitride film 208.
FIGS. 2A and 2B are plan views of the holes 206a and 206b drawn based on an SEM (scanning electron microscope) image viewed from above. As depicted in these figures, the upper ends 206c of holes 206a and 206b are each formed in a relatively fine circular shape, whereas their lower ends 206d are each formed in an unstable planar shape, and the lower ends 206d have the diameter smaller than the corresponding upper end 206c.
In this manner, when the stacked film including the silicon nitride film 208 is formed as the capacitor protection insulating film 210, the holes 206a and 206b cannot be formed in fine shapes. This causes a problem that the contact resistances of the conductive plugs 211a and 211b filled in these holes 206a and 206b become unstable.
FIG. 3 is an enlarged cross-sectional view of an essential part of another example of the semiconductor device disclosed in the Japanese Laid-open Patent Publication No. 2006-49795.
This semiconductor device differs from the example of FIG. 1 in that alumina films 220, 222, and 224 and silicon oxide films 221 and 223 are stacked as a capacitor protection insulating film 225 as depicted in FIG. 3.
In this example, a silicon nitride film is not included in the capacitor protection insulating film 225. Therefore, the etching for the holes 206a and 206b is easier than that in the example of FIG. 1.
However, the silicon oxide films 221 and 223 are formed by a plasma CVD (chemical vapor deposition) method which easily generates a tensile stress in a film. Accordingly, a semiconductor substrate 200 is easily warped in a recessed state due to the tensile stresses generated in the silicon oxide films 221 and 223. This causes another problem that a stress is applied to the ferroelectric capacitor Q serving as a piezoelectric element, and therefore makes it likely to deteriorate the ferroelectricity of the ferroelectric capacitor Q.